Acoe201_lab1 (4).doc Official

: Understanding the structure of Configurable Logic Blocks (CLBs) and programmable interconnects.

: Students typically use the Xilinx Spartan-3E Starter Kit, which features an FPGA, LEDs, buttons, and switches. ACOE201_Lab1 (4).doc

: Configuring the Xilinx ISE environment and creating a new project. : Understanding the structure of Configurable Logic Blocks

The primary objective of this lab is to familiarize students with the hardware and software environment used throughout the semester to design and verify a simple CPU. The primary objective of this lab is to

: Assigning package pins to connect design inputs/outputs to the physical switches and LEDs on the Spartan-3E board to verify the circuit works in real-time.

: Learning the process of writing hardware descriptions, simulating behavior, and downloading the configuration to physical hardware. Common Lab Exercises

: The Xilinx ISE Design Suite is used for developing and synthesizing digital circuits. Core Concepts :